1. Field of the Invention
The present invention relates to the field of computer systems and to memory systems for use therein. More particularly the present invention relates to a method and apparatus for dynamically allocating a portion of main memory within a variable amount of cache memory.
2. Description of Related Art
The performance of computer central processing units (CPU's) has increased dramatically in recent years and has far exceeded that of any corresponding increase in the performance of main memory DRAM. Not until the introduction of cache memory, was the performance of systems with DRAM main memory improved. This performance improvement was achieved by making a high speed, locally accessed copy of memory available to the CPU so that even during memory accesses the CPU would not always need to operate at the slower speeds of the system bus and the main memory DRAM. This method of copying memory is referred to as caching a memory system, and is a technique made possible by virtue of the fact that much of the CPU access, as determined by the computer source code, is in highly repetitive address spaces, which once copied from memory to cache can be utilized through many bus cycles before needing to be updated with the next address block. This method of memory copying is advantageous on the read cycles of the computer, which studies have shown, in contrast to the write cycles, constitute about 90% of the external accesses of the CPU.
The most popular hardware realization of a cache memory incorporates a high speed SRAM cache and a slow but less expensive DRAM main memory. A proprietary enhanced DRAM (EDRAM) chip developed by Ramtron International Corporation, 1850 Ramtron Drive, Colorado Springs, Colo. 80921, incorporates both these memories on one chip. Access to the chip is provided by a single bus. The product line is outlined in that company's "Specialty Memory Products Data Book," October, 1994, which is herein incorporated by reference.
Caching implementation to date has involved a full DRAM main memory implementation with a separate SRAM cache feature, usually this latter on the local bus and the former on a system bus, or a full EDRAM implementation with the EDRAM connected to the system bus. In either implementation a row of main memory maps to a full row of cache irregardless of the uniformity of memory access demands across the cached row.
To date there has been no caching system which allocates scarce cache resources on the basis of the probability of demand. This fact ends up retarding development of low cost hybrid main memory systems. What is needed is a way to combine main memory with an intelligently managed cache resource.